View NCV7517B_9064844.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2016 june, 2016 ? rev. 2 1 publication order number: NCV7517B/d NCV7517B flexmos hex low-side mosfet pre-driver the NCV7517B programmable six channel low?side mosfet pre?driver is one of a family of flexmos tm automotive grade products for driving logic?level mosfets. the product is controllable by a combination of serial spi and parallel inputs. it features programmable fault management modes and allows power?limiting pwm operation with programmable refresh time. the device offers 3.3 v/5.0 v compatible inputs and the serial output driver can be powered from either 3.3 v or 5.0 v. power?on reset provides controlled powerup and two enable inputs allow all outputs to be simultaneously disabled. each channel independently monitors its external mosfet?s drain voltage for fault conditions. shorted load fault detection thresholds are fully programmable using an externally programmed reference voltage and a combination of four discrete internal ratio values. the ratio values are spi selectable and allow different detection thresholds for each group of three output channels. fault information for each channel is 2?bit encoded by fault type and is available through spi communication. fault recovery operation for each channel is programmable and may be selected for latch?off or automatic retry. the flexmos family of products offers application scalability through choice of external mosfets. features ? 16?bit spi with frame error detection ? 3.3 v/5.0 v compatible parallel and serial control inputs ? 3.3 v/5.0 v compatible serial output driver ? two enable inputs ? open?drain fault and status flags ? programmable ? shorted load fault detection thresholds ? fault recovery mode ? fault retry timer ? flag masking ? load diagnostics with latched unique fault type data ? shorted load ? open load ? short to gnd ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant benefits ? scalable to load by choice of external mosfet lqfp32 ft suffix case 561ab www. onsemi.com marking diagram device package shipping ? ordering information NCV7517Bftg lqfp (pb?free) 250 units/tray ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. NCV7517B awlyywwg a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package NCV7517Bftr2g lqfp (pb?free) 2000 tape & ree l
NCV7517B www. onsemi.com 2 driver vcc2 v ss channel 0 flag mask power on reset & bias disable mode refresh/ref fault bits spi 16 bit fault logic & refresh timer clock vss vss vss vss vss fault reference generator ch 0?2 ch 3?5 ? + oa 6 12 2 4 vcc por csb sclk si so driver v ss iref iref iref iref iref NCV7517B hex mosfet pre?driver drn0 in0 in1 in2 in3 in4 in5 vcc2 gat0 drn1 gat1 channel 1 drn ref disable parallel serial vcc2 ena 1 ena 2 drn2 gat2 channel 2 drn ref disable parallel serial vcc2 ena 1 ena 2 drn3 gat3 channel 3 drn ref disable parallel serial vcc2 ena 1 ena 2 drn4 gat4 channel 4 drn ref disable parallel serial vcc2 ena 1 ena 2 drn5 gat5 channel 5 drn ref disable parallel serial vcc2 ena 1 ena 2 vss stab fltref gnd fltb si sclk csb vcc1 ena2 so vdd v ss fault detect ena1 drain feedback monitor por drn 0:5 mask 0:5 ena 1 gate select por ena1 figure 1. block diagram
NCV7517B www. onsemi.com 3 rx1 drn0 vcc2 gat0 drn1 gat1 vcc1 gat2 drn3 gat3 drn4 gat4 drn5 gat5 vss drn2 so gnd stab fltref in0 in1 in2 in3 in4 in5 csb sclk si fltb r d0 r d1 r d2 r d3 r d4 r d5 vdd ena1 nid9n05cl nid9n05cl nid9n05cl nid9n05cl nid9n05cl nid9n05cl cb2 cb1 NCV7517B unclamped load v load m 5w 28w 28w 14w 14w r filt +5v ena2 rx2 power?on reset +5v or +3.3v parallel spi irq host controller rst i/o r fpu r spu figure 2. application diagram
NCV7517B www. onsemi.com 4 pin function description symbol description fltref analog fault detect threshold: 5.0 v compliant drn0 ? drn5 analog drain feedback: internally clamped gat0 ? gat5 analog gate drive: 5.0 v compliant ena1, ena2 digital master enable inputs: 3.3 v/5.0 v (ttl) compatible in0 ? in5 digital parallel input: 3.3 v/5.0 v (ttl) compatible csb digital chip select input: 3.3 v/5.0 v (ttl) compatible sclk digital shift clock input: 3.3 v/5.0 v (ttl) compatible si digital serial data input: 3.3 v/5.0 v (ttl) compatible so digital serial data output: 3.3 v/5.0 v compliant stab digital open?drain output: 3.3 v/5.0 v compliant fltb digital open?drain output: 3.3 v/5.0 v compliant vcc1 power supply ? low power path gnd power return ? low power path ? device substrate vcc2 power supply ? gate drivers vdd power supply ? serial output driver vss power return ? vcc2, vdd, drain clamps 2 3 4 5 6 7 8 1 in0 in1 in2 in3 in4 in5 ena2 ena1 10 11 12 13 14 15 16 9 fltb csb sclk si so vdd stab vss 23 22 21 20 19 18 17 24 drn2 gat2 drn3 gat3 drn4 gat4 drn5 gat5 31 30 29 28 27 26 25 32 gnd fltref vcc1 vcc2 drn0 gat0 drn1 gat1 NCV7517B figure 3. 32 pin lqfp pinout (top view)
NCV7517B www. onsemi.com 5 maximum ratings (voltages are with respect to device substrate.) rating value unit dc supply (v cc1 , v cc2 , v dd ) ?0.3 to 6.5 v difference between v cc1 and v cc2 0.3 v difference between gnd (substrate) and v ss 0.3 v output voltage (any output) ?0.3 to 6.5 v drain feedback clamp voltage (note 1) ?0.3 to 47 v drain feedback clamp current (note 1) 10 ma input voltage (any input) ?0.3 to 6.5 v junction t emperature, t j ?40 to 150 c storage temperature, t stg ?65 to 150 c peak reflow soldering temperature: lead?free 60 to 150 seconds at 217 c (note 2) 260 peak c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. attributes characteristic value esd capability human body model machine model 2.0 kv 200 v moisture sensitivity (note 2) msl2 package thermal resistance (note 3) junction?to?ambient, r ja junction?to?pin, r jl 86.0 c/w 58.5 c/w 1. an external series resistor must be connected between the mosfet drain and the feedback input in the application. total clamp power dissipation is limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances. 2. for additional information, see or download on semiconductor?s soldering and mounting techniques reference manual, solderrm/d , and application note and8003/d. 3. values represent still air steady?state thermal performance on a 4 layer (42 x 42 x 1.5 mm) pcb with 1 oz. copper on an fr4 substrate, using a minimum width signal trace pattern (384 mm 2 trace area). recommended operating conditions symbol parameter min max unit v cc1 main power supply v oltage 4.75 5.25 v v cc2 gate drivers power supply v oltage v cc1 ? 0.3 v cc1 + 0.3 v v dd serial output driver power supply v oltage 3.0 v cc1 v v in high logic high input v oltage 2.0 v cc1 v v in low logic low input v oltage 0 0.8 v t a ambient still?air operating t emperature ?40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond th e recommended operating ranges limits may affect device reliability.
NCV7517B www. onsemi.com 6 electrical characteristics (4.75 v v ccx 5.25 v, v dd = v ccx , ?40 c t j 125 c, unless otherwise specified.) (note 4) characteristic symbol conditions min typ max unit v cc1 supply operating current ? v cc1 = 5.25 v, v fltref = 1.0 v ena x = 0 ena 1 = ena 2 = v cc1 , v drnx = 0 v, gat x drivers of f ena 1 = ena 2 = v cc1 , gat x drivers on ? ? ? 2.80 3.10 2.80 5.0 5.0 5.0 ma power?on reset threshold v cc1 rising 3.65 4.20 4.60 v power?on reset hysteresis ? 0.150 0.385 ? v digital i/o v in high ena x , in x , si, sclk, csb 2.0 ? ? v v in low ena x , in x , si, sclk, csb ? ? 0.8 v v in hysteresis ena x , in x , si, sclk, csb 100 330 500 mv input pullup current csb v in = 0 v ?25 ?10 ? a input pulldown current ena2, in x , si, sclk, v in = v cc1 ? 10 25 a input pulldown resistance ena1 100 150 200 k so low voltage v dd = 3.3 v, i sink = 5.0 ma ? 0.11 0.25 v so high voltage v dd = 3.3 v, i source = 5.0 ma v dd ? 0.25 v dd ? 0.11 ? v so output resistance output high or low ? 22 ? so tri?state leakage current csb = 3.3 v ?10 ? 10 a stab low voltage stab active, i stab = 1.25 ma ? 0.1 0.25 v stab leakage current v stab = v cc1 ? ? 10 a fltb low voltage fltb active, i fltb = 1.25 ma ? 0.1 0.25 v fltb leakage current v fltb = v cc1 ? ? 10 a fault detection ? gat x on fltref input current v fltref = 0 v ?1.0 ? ? a fltref input linear range (note 5) 0 ? v cc1 ? 2.0 v fltref op?amp v cc1 psrr (note 5) 30 ? ? db drn x clamp v oltage v cl i drnx = 10 a i drnx = i cl(max) = 10 ma 27 ? 34 42 ? 47 v drn x shorted load threshold gat x output high v fltref = 1.0 v register 2: r 1 = 0, r 0 = 0 or r 4 = 0, r 3 = 0 20 25 30 % v fltref register 2: r 1 = 0, r 0 = 1 or r 4 = 0, r 3 = 1 45 50 55 % v fltref register 2: r 1 = 1, r 0 = 0 or r 4 = 1, r 3 = 0 70 75 80 % v fltref register 2: r 1 = 1, r 0 = 1 or r 4 = 1, r 3 = 1 95 100 105 % v fltref drn x input leakage current v cc1 = v cc2 = v dd = 5.0 v, ena x = in x = 0 v, v drnx = v cl(min) v cc1 = v cc2 = v dd = 0 v, ena x = in x = 0 v, v drnx = v cl(min) ?1.0 ? 1.0 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not b e 100% parametrically tested in production. 5. guaranteed by design.
NCV7517B www. onsemi.com 7 electrical characteristics (continued) (4.75 v v ccx 5.25 v, v dd = v ccx , ?40 c t j 125 c, unless otherwise specified.) (note 6) characteristic symbol conditions min typ max unit fault detection ? gat x off drn x diagnostic current i sg short to gnd detection, v drnx = 0.30 v cc1 ?27 ?20 ?10 a i ol open load detection, v drnx = 0.75 v cc1 30 60 80 a drn x fault threshold v oltage v sg short to gnd detection 27 30 33 %v cc1 v ol open load detection 72 75 78 %v cc1 drn x off state bias v oltage v ctr ? ? 50 ? %v cc1 gate driver outputs gat x output resistance output high or low 200 350 500 gat x high output current v gatx = 0 v ?26.25 ? ?9.5 ma gat x low output current v gatx = v cc2 9.5 ? 26.25 ma turn?on propagation delay t p(on) in x to gat x (figure 4) ? ? 1.0 s csb to gat x (figure 5) turn?off propagation delay t p(off) in x to gat x (figure 4) ? ? 1.0 s csb to gat x (figure 5) output rise time t r 20% to 80% of v cc2 , c load = 400 pf (figure 4, note 5) ? ? 277 ns output fall time t f 80% to 20% of v cc2 , c load = 400 pf (figure 4, note 5) ? ? 277 ns fault t imers channel fault blanking t imer t bl(on) v drnx = 5.0 v; in x rising to fltb falling (figure 6) 11 21 31 s t bl(off) v drnx = 0 v; in x falling to fltb falling (figure 6) 90 120 150 s channel fault filter t imer t ff figure 7 7.0 12 17 s global fault refresh timer (auto?retry mode) t fr register 2: bit r 2 = 0 or r 5 = 0 7.5 10 12.5 ms register 2: bit r 2 = 1 or r 5 = 1 30 40 50 ms timer clock ena1 = 1 ? 500 ? khz serial peripheral interface (figure 9) v ccx = 5.0 v, v dd = 3.3 v, f sclk = 4.0 mhz, c load = 200 pf so supply voltage v dd 3.3 v interface 3.0 3.3 3.6 v 5.0 v interface 4.5 5.0 5.5 v sclk clock period ? ? 250 ? ns maximum input capacitance sl, sclk (note 7) ? ? 12 pf sclk high time sclk = 2.0 v to 2.0 v 125 ? ? ns sclk low time sclk = 0.8 v to 0.8 v 125 ? ? ns sl setup time sl = 0.8 v/2.0 v to sclk = 2.0 v (note 7) 25 ? ? ns sl hold time sclk = 2.0 v to sl = 0.8 v/2.0 v (note 7) 25 ? ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not b e 100% parametrically tested in production. 7. guaranteed by design.
NCV7517B www. onsemi.com 8 electrical characteristics (continued) (4.75 v v ccx 5.25 v, v dd = v ccx , ?40 c t j 125 c, unless otherwise specified.) (note 8) characteristic symbol conditions min typ max unit serial peripheral interface (continued) (figure 9) v ccx = 5.0 v, v dd = 3.3 v, f sclk = 4.0 mhz, c load = 200 pf so rise time (20% v so to 80% v dd ) c load = 200 pf (note 9) ? 25 50 ns so fall time (80% v so to 20% v dd ) c load = 200 pf (note 9) ? ? 50 ns csb setup time csb = 0.8 v to sclk = 2.0 v (note 9) 60 ? ? ns csb hold time sclk = 0.8 v to csb = 2.0 v (note 9) 75 ? ? ns csb to so time csb = 0.8 v to so data valid (note 9) ? 65 125 ns so delay time sclk = 0.8 v to so data valid (note 9) ? 65 125 ns transfer delay time csb rising edge to next falling edge (note 9) 1.0 ? ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not b e 100% parametrically tested in production. 9. guaranteed by design.
NCV7517B www. onsemi.com 9 in x gat x t p(off) 80% 20% t r 50% 50% t f t p(on) figure 4. gate driver timing diagram ? parallel input gat x t p(off) 50% csb 50% g x t p(on) figure 5. gate driver timing diagram ? serial input in x 50% drn x 50% fltb 50% t bl(on) t bl(off) figure 6. blanking timing diagram
NCV7517B www. onsemi.com 10 in x shorted load threshold drn x 50% fltb 50% t ff t ff open load threshold figure 7. filter timing diagram in x shorted load threshold (fl tref) drn x t bl(on) t ff gat x t fr t fr t bl(on) t fr figure 8. fault refresh timing diagram note: not defined but usually msb of data just received. csb setup csb sclk si so msb in lsb in msb out lsb out see note transfer delay 1 bits 14...1 bits 14...1 16 so delay si setup si hold csb hold so rise,fall 80% v dd 20% v dd csb to so valid figure 9. spi timing diagram
NCV7517B www. onsemi.com 11 detailed operating description general the NCV7517B is a six channel general purpose low?side pre?driver for controlling and protecting n?type logic level mosfets. while specifically designed for driving mosfets with resistive, inductive or lamp loads in automotive applications, the device is also suitable for industrial and commercial applications. programmable fault detection and protection modes allow the NCV7517B to accommodate a wide range of external mosfets and loads, providing the user with flexible application solutions. separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. on semiconductor?s smartdiscretes tm clamp mosfets, such as the nid9n05cl, are recommended when driving unclamped inductive loads. power up/down control the NCV7517B?s powerup/down control prevents spurious output operation by monitoring the v cc1 power supply. an internal power?on reset (por) circuit causes all gat x outputs to be held low until sufficient voltage is available to allow proper control of the device. all internal registers are initialized to their default states, fault data is cleared, and the open?drain fault (fltb) and status (stab) flags are disabled. when v cc1 exceeds the por threshold, outputs and flags are enabled and the device is ready to accept input data. when v cc1 falls below the por threshold during power down, flags are reset and disabled and all gat x outputs are driven and held low until v cc1 falls below about 0.7 v. spi communication the NCV7517B is a 16?bit spi slave device. spi communication between the host and the NCV7517B may either be parallel via individual csb addressing or daisy?chained through other devices using a compatible spi protocol. the active?low csb chip select input has a pullup current source. the si and sclk inputs have pulldown current sources. the recommended idle state for sclk is low. the tri?state so line driver can be supplied with either 3.3 or 5.0 v and is powered via the device?s v dd and v ss pins. the NCV7517B employs frame error detection that requires integer multiples of 16 sclk cycles during each csb high?low?high cycle (valid communication frame.) a frame error does not affect the flags. the csb input controls spi data transfer and initializes the selected device?s frame error and fault reporting logic. the host initiates communication when a selected device?s csb pin goes low. output (fault) data is simultaneously sent msb first from the so pin while input (command) data is received msb first at the si pin under synchronous control of the master?s sclk signal while csb is held low (figure 10). fault data changes on the falling edge of sclk and is guaranteed valid before the next rising edge of sclk. command data received must be valid before the rising edge of sclk. when csb goes low, frame error detection is initialized, latched fault data is transferred to the spi, and the fltb flag is disabled and reset if previously set. data for faults detected while csb is low are ignored but will be captured if still present after csb goes high. if a valid frame has been received when csb goes high, the last multiple of 16 bits received is decoded into command data, and fltb is re?enabled. latched (previous) fault data is cleared and current fault data is captured. the fltb flag will be set if a fault is detected. if a frame error is detected when csb goes high, new command data is ignored, and previous fault data remains latched and available for retrieval during the next valid frame. the fltb flag will be set if a fault (not a frame error) is detected. z z x x csb sclk si so 1 2 3 14 15 16 msb lsb b15 b14 b13 b12 ? b3 b2 b1 b0 ukn b15 b14 b13 b2 b1 b0 note: x=don?t care, z=tri?state, ukn=unknown data 4 ? 13 b12 ? b3 figure 10. spi communication frame format
NCV7517B www. onsemi.com 12 serial data and register structure the 16?bit data sent by the NCV7517B is always the encoded 12?bit fault information, with the upper 4 bits forced to zero. the 16?bit data received is decoded into a 4?bit address and a 6?bit data word (see figure 11). the upper four bits, beginning with the received msb, are fully decoded to address one of four programmable registers and the lower six bits are decoded into data for the addressed register. bit b15 must always be set to zero. the valid register addresses are shown in table 1. each register is next described in detail. channel fault output data ch0 ch1 ch2 ch3 ch4 ch5 0 0 0 0 b3 b2 b1 b0 msb lsb b7 b6 b5 b4 b11 b10 b9 b8 b15 b14 b13 b12 b3 b2 b1 b0 msb lsb b7 b6 b5 b4 b11 b10 b9 b8 b15 b14 b13 b12 register select command input data d3 d2 d1 d0 x x d5 d4 x x x x 0 a2 a1 a0 figure 11. spi data format table 1. register address definitions 4?bit address 6?bit input data b 15 a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 gate select 0 0 0 1 disable mode 0 0 1 0 refresh & reference 0 0 1 1 flag mask 0 1 x x null 16?bit output data b 15 b 14 b 13 b 12 b 11 b 0 0 0 0 0 d 11 12?bit fault data d 0 gate select ? register 0 each gat x output is turned on/off by programming its respective g x bit (see t able 2). setting a bit to 1 causes the selected gat x output to drive its external mosfet?s gate to v cc2 (on). setting a bit to 0 causes the selected gat x output to drive its external mosfet?s gate to v ss (off). note that the actual state of the output depends on por, ena x and shorted load fault states as later defined by equation 1. at powerup, each bit is set to 0 (all outputs off). table 2. gate select register a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 g 5 g 4 g 3 g 2 g 1 g 0 0 = gat x off 1 = gat x on disable mode ? register 1 the disable mode for shorted load faults is controlled by each channel?s respective m x bit (see t able 3). setting a bit to 1 causes the selected gat x output to latch?off when a fault is de tected. setting a bit to 0 causes the selected gat x output to auto?retry when a fault is detected. at powerup, each bit is set to 0 (all outputs in auto?retry mode). table 3. disable mode register a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 m 5 m 4 m 3 m 2 m 1 m 0 0 = auto?retry 1 = latch off refresh and reference ? register 2 refresh time (auto?retry mode) and shorted load fault detection references are programmable in two groups of three channels. refresh time and the fault reference for channels 5?3 is programmed by r x bits 5?3. refresh time and the fault reference for channels 2?0 is programmed by r x bits 2?0 (see table 4). at powerup, each bit is set to 0 (v flt = 25% v fltref , t fr = 10 ms).
NCV7517B www. onsemi.com 13 table 4. refresh and reference register a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 r 5 r 4 r 3 r 2 r 1 r 0 channels 5?3 channels 2?0 25% v fltref x 0 0 x 0 0 50% v fltref x 0 1 x 0 1 75% v fltref x 1 0 x 1 0 v fltref x 1 1 x 1 1 t fr = 10 ms x x x 0 x x t fr = 40 ms x x x 1 x x t fr = 10 ms 0 x x x x x t fr = 40 ms 1 x x x x x flag mask ? register 3 the drain feedback from each channel?s drn x input is combined with the channel?s k x mask bit (table 5). when k x = 1, a channel?s mask is cleared and its feedback to the fltb and stab flags is enabled. at powerup, each bit is set to 0 (all masks set). table 5. flag mask register a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 k 5 k 4 k 3 k 2 k 1 k 0 0 = mask set 1 = mask clear the stab flag is influenced when a mask bit changes clr set after one valid spi frame. fltb is influenced after two valid spi frames. this is correct behavior for fltb since, while a fault persists, the fltb will be set when csb goes lo hi at the end of an spi frame. the mask instruction is decoded after csb goes lo hi so fltb will only reflect the mask bit change after the next spi frame. both fltb and stab require only one valid spi frame when a mask bit changes set clr. null register ? register 4 fault information is always returned when any register is addressed. the null register (table 6) provides a way to read back fault information without regard to the content of d x . table 6. null register a 2 a 1 a 0 d 5 d 4 d 3 d 2 d 1 d 0 1 x x x x x x x x gate driver control and enable each gat x output may be turned on by either its respective parallel in x input or the internal g x (gate select) register bit via spi communication. the device?s common ena x enable inputs can be used to implement global control functions, such as system reset, overvoltage or input override by a watchdog controller. each parallel input and the ena2 input have individual internal pulldown current sources. the ena1 input has an internal pulldown resistor. unused parallel inputs should be connected to gnd and unused enable inputs should be connected to v cc1 . parallel input is recommended when low frequency ( 2.0 khz) pwm operation of the outputs is desired. ena2 disables all gat x outputs when brought low. when ena1 is brought low, all gat x outputs, the timer clock, and the flags are disabled. the fault and gate registers are cleared and the flags are reset. new serial g x data is ignored while ena1 is low but other registers can be programmed. when both the ena1 and ena2 inputs are high, the outputs will reflect the current parallel or serial input states. this allows ena1 to be used to perform a soft reset and ena2 to be used to disable the gat x outputs during initialization of the NCV7517B. the in x input state and the g x register bit data are logically combined with the internal (active low) power?on reset signal (por), the ena x input states, and the shorted load state (shrt x ) to control the corresponding gat x output such that: gat x por ena1 ena2 shrt x (in x g x ) (eq. 1)
NCV7517B www. onsemi.com 14 the gat x state truth table is given in table 7. table 7. gate driver truth table por ena1 ena2 shrt x in x g x gat x 0 x x x x x l 1 0 0 x x x l 1 0 1 x x x l 1 1 0 x x x l 1 1 1 1 0 0 l 1 1 1 1 1 x h 1 1 1 1 x 1 h 1 1 1 0 x x l 1 1 0 1 x x 0 l 1 1 1 0 x x g x l 1 1 0 1 x 0 g x g x gate drivers the non?inverting gat x drivers are symmetrical resistive switches (350 typ.) to the v cc2 and v ss voltages. while the outputs are designed to provide symmetrical gate drive to an external mosfet, load current switching symmetry is dependent on the characteristics of the external mosfet and its load. figure 12 shows the gate driver block diagram. driver vcc2 v ss v ss g x in x ena1 ena2 filter timer latch off / auto re?try m x d x1 drn x gat x s _ r r 2 | r 5 por fault detection d x0 t fr blanking timer encoding logic en shrt x 50 350 figure 12. gate driver channel fault diagnostics and behavior each channel has independent fault diagnostics and employs blanking and filter timers to suppress false faults. an external mosfet is monitored for fault conditions by connecting its drain to a channel?s drn x feedback input through an external series resistor. when either ena1 or ena2 is low, diagnostics are disabled. when both ena1 and ena2 are high, diagnostics are enabled. shorted load (or short to v load ) faults can be detected when a driver is on. open load or short to gnd faults can be detected when a driver is off. on?state faults will initiate mosfet protection behavior, set the fltb flag and the respective channel?s d x bits in the device?s fault latches. off?state faults will simply set the fltb flag and the channel?s d x bits. fault types are uniquely encoded in a 2?bit per channel format. fault information for all channels simultaneously is retrieved by spi read (figure 11). table 8 shows the fault?encoding scheme for channel 0. the remaining channels are identically encoded. table 8. fault data encoding channel 0 status d 1 d 0 0 0 no fault 0 1 open load 1 0 short to gnd 1 1 shorted load blanking and filter timers blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. filter timers are used to suppress glitches while a channel is in a stable state. a turn?on blanking timer is started when a channel is commanded on. drain feedback is sampled after t bl(on) . a turn?off blanking timer is started when a channel is commanded off. drain feedback is sampled after t bl(off) . a filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. drain feedback is sampled after t ff . blanking timers for all channels are started when both ena1 and ena2 go high or when either ena x goes high while the other is high. the blanking time for each channel depends on the commanded state when ena x goes high. while each channel has independent blanking and filter timers, the parameters for the t bl(on) , t bl(off) , and t ff times are the same for all channels. shorted load detection an external reference voltage applied to the fltref input serves as a common reference for all channels (figure 13). the fl tref voltage must be within the range of 0 to v cc1 ?2.0 v and can be derived via a voltage divider between v cc1 and gnd. shorted load detection thresholds can be programmed via spi in four 25% increments that are ratiometric to the applied fltref voltage. separate thresholds can be selected for channels 0?2 and for channels 3?5 (table 4).
NCV7517B www. onsemi.com 15 a shorted load fault is detected when a channel?s drn x feedback is greater than its selected fault reference after either the turn?on blanking or the filter has timed out. ? + oa r r r r 75% 50% 25% 0 2 x 4 decoder 1 2 3 0 2 x 4 decoder 1 2 3 channels 3?5 channels 0?2 r1 r0 r4 r3 register 2 bits fltref 0 ? 3v rx 1 rx 2 vcc1 vcc1 kelvin figure 13. shorted load reference generator shorted load fault recovery shorted load fault disable mode for each channel is individually spi programmable via the m x bits in the device?s disable mode register (table 3). when latch?off mode is selected the corresponding gat x output is turned off upon detection of a fault. fault recovery is initiated by toggling (on off on) the channel?s respective in x parallel input, serial g x bit, or ena2. when auto?retry mode is selected (default mode) the corresponding gat x output is turned off for the duration of the programmed fault refresh time (t fr ) upon detection of a fault. the output is automatically turned back on (if still commanded on) when the refresh time ends. the channel?s drn x feedback is resampled after the turn?on blanking time. the output will automatically be turned off if a fault is again detected. this behavior will continue for as long as the channel is commanded on and the fault persists. in either mode, a fault may exist at turn?on or may occur some time afterward. to be detected, the fault must exist longer than either t bl(on) at turn?on or longer than t ff some time after turn?on. the length of time that a mosfet stays on during a shorted load fault is thus limited to either t bl(on) or t ff . in auto?retry mode, a persistent shorted load fault will result in a low duty cycle (t fd t bl(on) /t fr ) for the affected channel and help prevent thermal failure of the channel?s mosfet. caution ? continuous input toggling via in x , g x or ena2 will override either disable mode. care should be taken to service a shorted load fault quickly when one has been detected. fault recovery refresh time refresh time for shorted load faults is spi programmable to one of two values for channels 0?2 (register bit r2) and for channels 3?5 (register bit r5) via the refresh and reference register (table 4). a global refresh timer with taps at nominally 10 ms and 40 ms is used for auto?retry timing. the first faulted channel triggers the timer and the full refresh period is guaranteed for that channel. an additional faulted channel may initially retry immediately after its turn?on blanking time, but subsequent retries will have the full refresh time period. if all channels in a group (e.g. channels 0?2) become faulted, they will become synchronized to the selected refresh period for that group. if all channels become faulted and are set for the same refresh time, all will become synchronized to the refresh period. open load and short to gnd detection a window comparator with fixed references proportional to v cc1 along with a pair of bias currents is used to detect open load or short to gnd faults when a channel is off. each channel?s drn x feedback is compared to the references after either the turn?off blanking or the filter has timed out. figure 14 shows the drn x bias and fault detection zones. the diagnostics are disabled and the bias currents are turned off when ena x is low. no fault is detected if the feedback voltage at drn x is greater than the v ol open load reference. if the feedback is less than the v sg short to gnd reference, a short to gnd fault is detected. if the feedback is less than v ol and greater than v sg , an open load fault is detected. v ctr v sg v ol ?i sg i ol 0 v drnx i drnx open load short to gnd no fault figure 14. drn x bias and fault detection zones figure 15 shows the simplified detection circuitry. bias currents i sg and i ol are applied to a bridge along with bias voltage v ctr (50% v cc1 typ.).
NCV7517B www. onsemi.com 16 b ? + cmp2 i ol + _ ? + cmp1 v ctr v ol v cc1 a v load (v cl ) 50 drn x r dx r load r sg v x 1600 i sg d1 d2 d3 d4 dz1 v sg +v os figure 15. short to gnd/open?load detection when a channel is off and v load and r load are present, r sg is absent, and v drnx >> v ctr , bias current i ol is supplied from v load to ground through external resistors r load and r dx , and through the internal 1650 resistance and bridge diode d2. bias current i sg is supplied from v cc1 to v ctr through d3. no fault is detected if the feedback voltage (v load minus the total voltage drop caused by i sg and the resistance in the path) is greater than v ol . when either v load or r load and r sg are absent, the bridge will self?bias so that the voltage at drn x will settle to about v ctr . an open load fault can be detected since the feedback is between v sg and v ol . short to gnd detection can tolerate up to a 1.0 v offset (v os ) between the NCV7517B?s gnd and the short. when r sg is present and v drnx << v ctr , bias current i sg is supplied from v cc1 to v os through d1, the internal 1650 , and the external r dx and r sg resistances. bias current i ol is supplied from v ctr to ground through d4. a ?weak? short to gnd can be detected when either v load or r load is absent and the feedback (v os plus the total voltage rise caused by i ol and the resistance in the path) is less than v ol . when v load and r load are present, a voltage divider between v load and v os is formed by r load and r sg . a ?hard? short to gnd may be detected in this case depending on the ratio of r load and r sg and the values of r dx , v load , and v os . note that the comparators see a voltage drop or rise due only to the 50 internal resistance and the bias currents. this produces a small difference in the comparison to the actual feedback voltage at the drn x input. several equations for choosing r dx and for predicting open load or short to gnd resistances, and a discussion of the dynamic behavior of the short to gnd/open load diagnostic are provided in the applications information section of this data sheet. status flag (stab) the open?drain active?low status flag output can be used to provide a host controller with information about the state of a channel?s drn x feedback. feedback from all channels is logically ored to the flag (figure 16). the stab outputs from several devices can be wire?ored to a common pullup resistor connected to the controller?s 3.3 or 5.0 v v dd supply. when ena1 is high, the drain feedback from a channel?s drn x input is compared to the v ol reference without regard to ena2 or the commanded state of the channel?s driver. the flag is reset and disabled when ena1 is low or when all mask bits are set. see table 9 for additional details. the flag is set (low) when the feedback voltage is less than v ol , and the channel?s mask bit (table 5) is cleared. the flag is reset (hi?z) when the feedback voltage is greater than v ol , and the channel?s mask bit is cleared. ? + cmp1 v ol a drn x k x ena1 por other channels 500 khz stab d q clr figure 16. stab flag logic fault flag (fltb) the open?drain active?low fault flag output can be used to provide immediate fault notification to a host controller. fault detection from all channels is logically ored to the flag (figure 17). the fltb outputs from several devices can be wire?ored to a common pullup resistor connected to the controller?s 3.3 or 5.0 v v dd supply. the flag is set (low) when a channel detects any fault, the channel?s mask bit (t able 5) is cleared, and both ena x and csb are high. the flag is reset (hi?z) and disabled when either ena1 or csb is low. see table 9 for additional details. k x other channels s q flt b fault x r por e na2 csb (reset dominant) ena1 figure 17. fltb flag logic
NCV7517B www. onsemi.com 17 fault detection and capture each channel of the NCV7517B is capable of detecting shorted load faults when the channel is on, and short to ground or open load faults when the channel is off. each fault type is uniquely encoded into two?bit per channel fault data. a drain feedback input for each channel compares the voltage at the drain of the channel?s external mosfet to several internal reference voltages. separate detection references are used to distinguish the three fault types, and blanking and filter timers are used respectively to allow for output state transition settling and for glitch suppression. fault diagnostics are disabled when either enable input is low. when both enable inputs are high, each channel?s drain feedback input is continuously compared to references appropriate to the channel? s input state to detect faults, but the comparison result is only latched at the end of either a blanking or filter timer event. blanking timers for all channels are triggered when either enable input changes state from low to high while the other enable input is high, or when both enable inputs go high simultaneously. a single channel?s blanking timer is triggered when its input state changes. if the comparison of the feedback to a reference indicates an abnormal condition when the blanking time ends, a fault has been detected and the fault data is latched into the channel?s fault latch. a channel?s filter timer is triggered when its drain feedback comparison state changes. if the change indicates an abnormal condition when the filter time ends, a fault has been detected and the fault data is latched into the channel?s fault latch. thus, a state c hange of the inputs (ena x , in x or g x ) or a state change of an individual channel?s feedback (drn x ) comparison must occur for a timer to be triggered and a detected fault to be captured. fault capture, spi communication, and spi frame error detection the fault capture and frame error detection strategies of the NCV7517B combine to ensure that intermittent faults can be captured and identified, and that the device cannot be inadvertently reprogrammed by a communication error. the NCV7517B latches a fault when it is detected, and frame error detection will not allow any register to accept data if an invalid frame occurred. when a fault has been detected, the fltb flag is set and fault data is latched into a channel?s fault latch. the latch captures and holds the fault data and ignores subsequent fault data for that channel until a valid spi frame occurs. fault data from all channels is transferred from each channel?s fault latch into the spi shift register and the fltb flag is reset when csb goes low at the start of the spi frame. fault latches are cleared and re?armed when csb goes high at the end of the spi frame only if a valid frame has occurred; otherwise the latches retain the detected fault data until a valid frame occurs. the fltb flag will be set if a fault is still present. fault latches for all channels and the fltb flag can also be cleared and re?armed by toggling ena1 h?l?h. a full i/o truth table is given in table 9. fault data readback examples several examples are shown to illustrate fault detection, capture and spi read?back of fault data for one channel. a normal spi frame returns 16 bits of data but only the two bits of serial data for the single channel are shown for clarity. the examples assume: ? the NCV7517B is configured as in figure 2 ? both enable inputs are high ? the channel?s flag mask bit is cleared ? disable mode is set to auto?retry ? the parallel input commands the channel ? spi frame is always valid shorted load detected refer to figure 18. the channel is commanded on when in x goes high. gat x goes high and the timers are started. at ?a?, the stab flag is set as the drn x feedback falls through the v ol threshold. a spi frame sent soon after the in x command returns data indicating ?no fault.? the blanking time ends and the filter timer is triggered as drn x rises through the fltref threshold. the stab flag is reset as drn x passes through the v ol threshold. drn x is nearly at v load when the filter time ends at ?b?. a shorted load fault is detected and captured by the fault latch, gat x goes low, the fltb flag is set, and the auto?retry timer is started. an spi frame sent soon after ?b? returns data indicating ?shorted load?. the fltb flag is reset when csb goes low. at ?c? when csb goes high at the end of the frame, the fault latch is cleared and re?armed. since in x and the drn x feedback are unchanged, fltb and the fault latch are set and the fault is recaptured. when the auto?retry timer ends at ?d?, gat x goes high and the blanking and filter timers are started. since in x and drn x are unchanged, gat x goes low when the blanking time ends at ?e? and the auto?retry timer is started. read?back data continues to indicate a ?shorted load? and the fltb flag continues to be set while the fault persists.
NCV7517B www. onsemi.com 18 0 1 11 00 11 0 1 0 1 fault latch blank timer filter timer t ff t bl(on) t fr t bl(on) 11 11 11 drnx inx 0 1 fltref 0 vload vol so fltb 0 1 0 1 csb 0 1 11 11 11 11 11 gatx 0 1 stab 0 1 b e a internal signals c 00 fault detected d t fr figure 18. shorted load detected
NCV7517B www. onsemi.com 19 shorted load recovery figure 19 is a continuation of figure 18. in x is high when the auto?retry timer ends. gat x goes high and the blanking and filter timers are started. the fault is removed before the blanking timer ends, and drn x starts to fall. as drn x passes through the v ol threshold at ?a?, the stab flag is set. drn x continues to fall and settles below the fltref threshold. an spi frame is sent during the blanking time and returns data indicating a ?shorted load? fault. although the fault is removed, updates to the fault latches are suppressed while a blanking or filter timer is active. the same fault is captured again and fltb is set when csb goes high. at ?b? the blanking time ends and the channel? s fault bits will indicate ?no fault? but because the latched data has not yet been read, the data remains unchanged. the spi frame sent after the blanking time ends returns a ?shorted load? fault because the previous frame occurred during the blanking time. since the channel?s fault bits indicate ?no fault?, fltb is reset and the fault latch is updated at ?c? when csb goes high. if another spi frame is sent before ?d?, the returned data will indicate ?no fault?. the channel is commanded off at ?d?. gat x goes low and the timers are started. drn x starts to rise and the stab flag is reset as drn x passes through the v ol threshold. the spi frame sent at ?e? returns data indicating ?no fault?. c fault removed a so gatx fltb inx 0 1 0 1 0 1 0 1 0 1 csb 0 1 11 00 0 1 0 1 11 11 11 drnx fltref 0 vload vol fault latch blank timer filter timer 11 11 t ff t bl(on) t fr internal signals stab 0 1 t bl(off) t ff 00 d e b figure 19. shorted load recovery
NCV7517B www. onsemi.com 20 short to gnd/open load figure 20 illustrates turn?off with an open or high resistance load when some capacitance is present at drn x . in the case of an open load, drn x rises and settles to v ctr . in the case of a high resistance load, drn x may continue to rise and may eventually settle to v load . the channel is commanded off. gat x goes low and the timers are started. drn x starts to rise and is below the v sg threshold when the blanking time ends at ?a?. a short to gnd fault is detected and captured by the fault latch, and the fltb flag is set. drn x continues to rise and as it passes through the v sg threshold at ?b?, the filter timer is triggered. at the end of the filter time, the channel?s fault bits will indicate an ?open load? but because the latched data has not yet been read, the data remains unchanged. an spi frame sent shortly after ?b? returns data indicating ?short to gnd? and the fault latch is updated at ?c? when csb goes high. the next three frames sent after ?c? return data indicating an ?open load?. the stab flag is reset at ?d? as drn x passes through the v ol threshold. note that the filter timer is not triggered as drn x passes from a fault state to a good state. the channel?s fault bits will indicate ?no fault? but because the latched data has not yet been read, the data remains unchanged. the fault latch is updated at ?e? when csb goes high and the fltb flag remains reset. the next spi frame sent returns data indicating ?no fault?. so fltb 0 1 0 1 0 1 csb 0 1 00 0 1 0 1 10 01 00 00 10 01 01 01 00 internal signals fault latch blank timer filter timer 01 01 t ff t ff t bl(off) gatx 0 1 drnx vsg 0 vload vctr vol a b c d inx 0 1 stab 0 1 e figure 20. short to gnd/open load
NCV7517B www. onsemi.com 21 table 9. i/o truth table inputs outputs* por ena1 ena2 csb k x in x g x drn x gat x fltb stab d x1 d x0 comment 0 x x x 0 x 0 x l z z 00 por reset 1 0 x x x x x x l z z 00 ena1 1 1 0 x k x x g x x l fltb stab d x1 d x0 ena2 1 1 0 1 x k x x 0 x l z z 00 ena1 reset 1 1 1 0 x k x x g x x l fltb stab d x1 d x0 ena2 disable 1 1 x x 0 x x x l z z ? flags masked 1 1 0 x 1 x x > v ol l ? z ? stab reset 1 1 0 x 1 x x < v ol l ? l ? stab set 1 1 0 x 1 0 x x < v ol l ? l z ? stab reset 1 1 0 x 0 1 x x < v ol l ? z l ? stab set 1 1 1 x 1 0 0 > v ol l z z 00 flags reset 1 1 1 1 1 0 0 v sg v ol l l z 11 stab reset 1 1 1 x 1 x 1 < v fltref h z l 00 stab set 1 1 1 1 1 x 1 v fltref v ol l l z 11 stab reset * output states after blanking and filter timers end and when channel is set to latch?off mode.
NCV7517B www. onsemi.com 22 application guidelines general unused drn x inputs should be connected to v cc1 to prevent false open load faults. unused parallel inputs should be connected to gnd and unused enable inputs should be connected to v cc1 . the mask bit for each unused channel should be ?set? (see table 5) to prevent activation of the flags and the user?s software should be designed to ignore fault information for unused channels. for best shorted?load detection accuracy, the external mosfet source terminals should be star?connected and the NCV7517B?s gnd pin, and the lower resistor in the fault reference voltage divider should be kelvin connected to the star (see figures 2 and 13). consideration of auto?retry fault recovery behavior is necessary from a power dissipation viewpoint (for both the NCV7517B and the mosfets) and also from an emi viewpoint. driver slew rate and turn?on/off symmetry can be adjusted externally to the NCV7517B in each channel?s gate circuit by the use of series resistors for slew control, or resistors and diodes for symmetry. any benefit of emi reduction by this method comes at the expense of increased switching losses in the mosfets. the channel fault blanking timers must be considered when choosing external components (mosfets, slew control resistors, etc.) to avoid false faults. component choices must ensure that gate circuit charge/discharge times stay within the turn?on/turn?off blanking times. the NCV7517B does not have integral drain?gate flyback clamps. clamp mosfets, such as on semiconductor?s nid9n05cl, are recommended when driving unclamped inductive loads. this flexibility allows choice of mosfet clamp voltages suitable to each application. drn x feedback resistor each drn x feedback input has a clamp to keep the applied voltage below the breakdown voltage of the NCV7517B. an external series resistor (r dx ) is required between each drn x input and mosfet drain. channels may be clamped sequentially or simultaneously but total clamp power is limited to the maximum allowable junction temperature. to limit power in the drn x input clamps and to ensure proper open load or short to gnd detection, the r dx resistor must be dimensioned according to the following constraint equations: r dx(min) v pk ?v cl(min) i cl(max) (eq. 2) r dx(max) v sg ? | v os | | i sg | (eq. 3) where v pk is the peak transient drain voltage, v cl is the drn x input clamp voltage, i cl(max) is the input clamp current, and v sg and i sg are the respective short to gnd fault detection voltage and diagnostic current, and v os is the allowable offset (1.0 v max) between the NCV7517B?s gnd and the short. once r dx is chosen, the open load and short to gnd detection resistances in the application can be predicted: r ol v load ?v ol i ol r dx (eq. 4) r sg r load (v sg v os ? | i sg | r dx ) v load ?v sg | i sg | (r dx r load ) (eq. 5) using the data sheet values for v cl(min) = 27 v, i cl(max) = 10 ma, and choosing v pk = 55 v as an example, equation 2 evaluates to 2.8 k minimum. choosing v cc1 = 5.0 v and using the typical data sheet values for v sg = 30%v cc1 , i sg = 20 a, and choosing v os = 0, equation 3 evaluates to 75 k maximum. selecting r dx = 6.8 k 5%, v cc1 = 5.0 v, v load = 12.0 v, v os = 0 v, r load = 555 , and using the typical data sheet values for v ol , i ol , v sg , and i sg , equation 4 predicts an open load detection resistance of 130.7 k and equation 5 predicts a short to gnd detection resistance of 71.1 . when r dx and the data sheet values are taken to their extremes, the open load detection range is 94.1 k r ol 273.5 k , and the short to gnd detection range is 59.2 r sg 84.4 .
NCV7517B www. onsemi.com 23 package dimensions lqfp32, 7x7 case 561ab issue o
NCV7517B www. onsemi.com 24 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates , and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or dea th associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semicon ductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCV7517B/d flexmos and smartdiscretes are trademar ks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative

▲Up To Search▲

Price & Availability of NCV7517B

	To Download NCV7517B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .